Power-up circuits formed in an integrated circuit chip for providing a power-up pulse to the same chip or other integrated circuit chips are well-known in the art. One type of a power-up circuit includes a resistor and a capacitor connected in series to a supply voltage with the junction between the resistor and capacitor connected to the input of an inverter. When power is first applied to the power-up circuit, the capacitor starts to charge. While charging, the inverter outputs a logic high state. When the capacitor is sufficiently charged to produce a logic high state, the output of the inverter switches to a logic low state. The sequentially generated logic high and low states define a power-up pulse for driving the integrated circuit chips.
One disadvantage of the prior art power-up circuit is that when the supply voltage ramps up relatively slowly compared with the charging rate of the capacitor, the output of the capacitor tracks the supply voltage, and the output of the power-up circuit always stays at the logic low state. As a result, no pulse is produced, and power-up failure occurs. To ensure a proper power-up pulse over a wider range of the ramp-up rate of the supply voltage, larger capacitors have been used in power-up circuits. This, however, has created a problem under multiple power-up and power-down situations within a short period of time. Specifically, since the larger capacitor discharges very slowly, it may be only partially discharged. As a result, no power-up pulse is generated from the second power-up. Another disadvantage is that the prior an power-up circuit is highly susceptible to noise on the supply voltage. As is well-known in the art, the supply voltage level upon power-up is prone to power glitches as it rises from a reference ground to a steady supply voltage. These power glitches may cause no pulse or multiple pulses to be generated, both of which may result in a power-up failure.
It is therefore desirable to provide a power-up circuit that consistently produces a proper power-up pulse regardless of the ramp-up rate of, and power glitches on the supply voltage. It is also desirable to provide the power-up circuitry with a fast reset capability to provide the necessary power-up pulses under multiple power-up and power-down situations within a short period of time.